1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a method for fabricating a semiconductor device which is capable of preventing grooves from developing at an edge portion of the semiconductor device when using shallow trench isolation technology and thereby prevent the degradation of operational characteristics of a transistor.
2. Description of the Background Art
As semiconductor devices are becoming more highly integrated, a fine pattern is required to fabricate the device, and accordingly, a channel length of a transistor and a width of a field oxide film for element isolation are reduced. Thus, various techniques for element isolation have been proposed such as a LOCOS method, a modified LOCOS method, or a trench isolation method.
When the LOCOS method is used, the size of an active region is reduced due to an occurrence of a bird's beak phenomenon of an oxide film that grows extended over the active region during a thermal oxidation process. This makes it difficult to adjust the thickness of a gate oxide film. Thus, the LOCOS method has restricted application.
For this reason, instead of adopting the LOCOS process, the trench isolation ("TI") method is widely used. In the TI method, a silicon substrate is partly etched to form a trench on which an insulation film (i.e., an oxide film) is deposited. Then, the insulation film overlying the active region is etched by using an etch back process or a chemical mechanical polishing method so that the insulation film remains only in a field region.
FIGS. 1 through 6 illustrate a known process of a TI method for isolating a semiconductor device.
FIG. 1 depicts pad oxide film 12 formed of a thermal oxide film material and antioxidation film 14 formed of an SiN material. These two films are sequentially formed on semiconductor device, i.e., a silicon substrate 10.
As shown in FIG. 2, a photoresist film pattern (not shown) is formed on antioxidation film 14 in a manner such that the surface of a portion of antioxidation film 14 can be used as a field region. By using the photoresist film pattern as a mask, antioxidation film 14 and pad oxide film 12 are sequentially etched. Then, the photoresist film pattern is removed so that only antioxidation film 14 and pad oxide film 12 remain on the active region where an active device is to be formed. Subsequently, by using the etched antioxidation film 14 as a mask, the exposed portion of substrate surface 10 is etched to a predetermined thickness to thereby form a trench t.
According to FIG. 3, first insulation film 16 formed of a thermal oxide film material is deposited along the internal interface of trench t. The reason why the first insulation film 16 is formed inside trench t is to compensate for any damage on the etched surface of silicon substrate 10, which may be possibly caused during the etching process.
Successively, stress buffer film 18, made of an SiN material ("nitride film liner"), is formed on the entire surface of the resulting structure, and second insulation film 20, made of a USG material, is formed on stress buffer film 18 including trench t, sufficiently filling the trench.
As shown in FIG. 4, the second insulation film 20 is CMP ("chemical and mechanical polishing") processed to leave antioxidation film 14 with a predetermined thickness on the active region, thereby making the entire substrate planar. During this process, stress buffer film 18 is also partly etched.
FIGS. 5 and 5A illustrate antioxidation film 14 on the active region being removed by using an isotropic etching process, during which stress buffer film 18, at the upper end portion of the second insulation film 20, is also partly etched forming groove g1.
FIGS. 6 and 6A show pad oxide film 12 of the active region being removed by a wet etching method, forming a shallow trench isolation ("STI") consisting of stress buffer film 18 and first and second insulation layers 16 and 20. Further, after a buffer oxide film (not shown) is formed on the active region of the substrate 10, an ion implantation process for forming a well and an ion implantation process for controlling a threshold voltage Vth are performed, and then the buffer oxide film is removed, thereby completing the element isolation process.
Since second insulation film 20 of the field region is also partly etched to form groove g2 during the process of removing pad oxide film 12 and the buffer oxide film, the element isolation process is completed, and the step coverage of the STI is at a level almost the same as that of the active region. However, the STI formed according to the above method has the following problems relating to the fabrication of the device. Since the buffer film 18 inside the trench t is also partly etched during the process of removing antioxidation film 14, groove g1, having a concave shape, is undesirably formed between first insulation film 16 and the second insulation film 20 both forming the STI in the vicinity of the interface of the active region and the field region. Moreover, the groove g1 becomes larger during the process of removing the pad oxide film 12. FIGS. 5A and 6A show an enlarged view of the portions I and II in FIGS. 5 and 6, respectively, where the grooves g1 and g2 are formed.
When a transistor is formed as a gate electrode substance by deposition at the portion where the grooves g1 and g2 are formed, an electric field is concentrated on that part where the grooves are formed when the device is driven, thus causing the gate oxide film to be degraded. In a worst case scenario, a hump phenomenon occurs in which the transistor appears to have two threshold voltages Vth, resulting in deteriorated characteristics of the transistor.